The present invention relates generally to the packaging of integrated circuits. More particularly, the invention relates to leadless packaging designs and processes.
A leadless lead frame package is an integrated circuit package design that contemplates the use of a lead frame in the formation of a chip scale package. The resulting packages are sometimes referred to as quad flat packsxe2x80x94no lead packages. As illustrated in FIGS. 1A-1C, in typical leadless lead frame packages, a copper lead frame strip or panel 101 is patterned (typically by stamping or etching) to define a plurality of arrays 103 of device areas 105. Each device area 105 includes a die attach pad 107 and a plurality of contacts 109 disposed about their associated die attach pad 107. Very fine lie bars 108 and 111 are generally used to support the die attach pad 107 and contacts 109, respectively. The contacts 109 are generally attached to the tie bars 111 by tie bar stubs 112.
During assembly, dice are attached to the respective die attach pads 107. Conventional wire bonding is used to electrically couple bond pads on each die to their associated contacts 109 on the lead frame strip 101. After the wire bonding, a plastic cap is molded over the top surface of each array 103 of wire-bonded dice. The dice are generally then singulated and tested using conventional sawing and testing techniques.
Since leadless lead frame packaging has proven to be a cost effective packaging arrangement, there are continuing efforts to provide further improvements to the package structure and/or processing, to permit the package style to be used in additional applications and/or to improve specific characteristics of the resultant devices.
To achieve the foregoing and other objects of the invention, methods of fabricating leadless packages are described that facilitate increased contact density. In most respects, the packages may be fabricated in a manner similar to current lead frame based leadless packaging techniques. By way of example, a lead frame panel may be patterned to define a plurality of device areas and a matrix of tie bars. Each device area includes a die attach pad and a multiplicity of conductive contacts. The contacts may each be attached to an associated tic bar by a tie bar stub. In the present invention, the die attach pad is supported by the contacts. In a preferred embodiment, the die attach pad is carried by support bars that extend from selected contacts. The use of die attach pad support bars eliminates the need for separate tie bars to support the die attach pad during fabrication thus increasing the available space for additional contacts. In one embodiment of the invention, the support bars are narrower than their corresponding contacts while in other embodiments the support bars are equal to or wider than their corresponding contacts.
During assembly, the lead frame panel is held in position by vacuum or any other suitable means while the die attach pad support bars are severed. The position holding device may be an integrated part of existing taping machinery, or may stand alone as a separate fixture. Severing the die attach pad support bars may be accomplished in any of a number of manners well known in the art including, but not limited to, punching, stamping, sawing, laser cutting, or etching. Once the die attach pad support bars are severed, an adhesive tape is adhered to the exposed surface of the lead frame panel so that the die attach pad may be held in a fixed position relative to its associated contacts.
After the adhesive tape has been applied, the packages may be assembled in any appropriate manner. By way of example, dice may be attached to the die attach pads and electrically connected to the contacts (e.g., by wire bonding). Thereafter, a casing is molded or otherwise provided that encapsulates the die and connectors while leaving the bottom surfaces of the contacts exposed. After the encapsulation, device areas are singulated into individual units. This method may be applied equally to both one-dimensional arrays of device areas as well as to two-dimensional arrays of device areas.